1. Field of the Invention
The present invention relates to the field of stored program, electronic digital computer memory systems and in particular to a system for the addressing of multibank memory systems.
2. Description of the Prior Art
In the prior art, it is known that digital computer systems incorporate very large capacity main memory systems that are comprised of a plurality of memory banks. Each memory bank is generally identical to every other memory bank in the memory system in operating speed and capacity, i.e., each bank incorporates the same number of addressable memory locations, each addressable memory location being capable of storing the same number of binary digits, or bits.
In prior art computer systems, it is generally the practice that data, i.e., the number of binary digits that make up the multi-bit words that are stored at each addressable memory location of the memory system, is transferred into or out of the associated memory system in successive memory requests from successive addressable memory locations. However, with the advent of the state of the art scientific processors that perform successive memory requests at very high addressing rates, e.g., once every 30 nanoseconds (ns), it has been found that the addressing rate or memory request frequency, of the scientific processor is now several times faster than the access rate, or cycle time, of the memory system. That is, a scientific processor may be capable of coupling successive addresses to an associated memory system every 30 ns while the associated memory system may not be capable of reading the data words out of the addressed memory locations at a rate greater than every, i.e., having a memory access time of, 240 ns.
In the prior art it is known to form a memory system of B memory banks, where B=2.sup.X, where X is a positive integer. This is so, as the digital computer system operates in the binary number system wherein translation of the number B to a specific memory bank number is logically optimal while yet utilizing the full range of the number of bits that represent the number B. That is, in a memory system having 8 (8=2.sup.3) memory banks, the binary representation of each of the 8 memory banks is: memory bank 0 is represented by the binary number 000; memory bank 7 is represented by the binary number 111.
In such state of the art digital computer systems incorporating scientific processors, it has been the practice to utilize an addressing scheme whereby successive memory locations in the memory system are spread across the B=8 memory banks. That is, in a memory system in which B=8, data word 0 would be stored in memory location 0 of memory bank 0, data word 1 would be stored in memory location 0 of memory bank 1, etc., until data word 7 would be stored in memory location 0 of memory bank 7 after which the sequence would repeat and data word 8 would be stored in memory location 1 of memory bank 0, data word 9 would be stored in memory location 1 of memory bank 1, etc. until data word 16 would be stored in memory location 1 of memory bank 7, etc. Such a state of the art digital computer system is disclosed in the copending patent application ERA-3022 of James H. Scheuneman entitled High Performance Storage Unit having a filing data of Mar. 30, 1984, and a Ser. No. of 596,130 which patent application is assigned to the Sperry Corporation as is the present patent application, the teachings of which copending patent application are incorporated herein by reference.
Because, as discussed herein above, such state of the art scientific processors have address cycle times that are as short as, e.g., 30 ns and that are several times shorter than the memory cycle time, e.g., 240 ns, of the associated memory system, it is statistically quite possible that the scientific processor may attempt to address a memory location in a memory bank that the scientific processor has addressed within a previously initiated memory cycle time of, e.g., 240 ns. If such an attempt is made, a "memory stacking condition" occurs for which the scientific processor would be placed in a "waiting condition" until the previous memory cycle has been completed. This waiting condition provides a serious degradation of scientific processor performance. It is an object of the present invention to provide a novel system for addressing a multibank memory system whereby such performance degradation is minimized.
In such state of the art computer systems, the scientific processor operates under the control of computer programs that address the associated memory system in sequences of successive memory addresses that are incremented by a fixed number that is a power of 2, e.g., 4, as in successive memory addresses 0, 3, 7, 11, etc. This incrementation of, or separation between, successive memory addresses is called the "stride" of the computer program, and, although it is fixed for each computer program, different computer programs may have different strides.